This invention relates to monolithic integrated circuit devices, their structure, and preparation, and particularly to the fabrication of the emitter region of very shallow devices.
The progress in solid state technology is largely determined by the ability to control and modify material parameters in a well defined manner. Semiconductors are a typical example, where minute traces of impurities will markedly influence the electrical properties. The concept of introducing dopants into semiconductors by means of high energetic particles is well known. This introduction of particles is commonly referred to as ion implantation which is defined as a process in which a beam of energetic particles is directed against a body of materials to selectively affect electrical and/or chemical changes in the body by the causing of the ions, of the beam, to pass into the body of the treated material.
Ion implantation of impurities into semiconductor substrates has a number of significant advantages in the fabrication of semiconductor devices over the more conventional introduction by thermal diffusion. Since ion implantation is not a high temperature process, a larger number of materials, including organic photoresists, can be used as masking for controlling the area of implantation into the substrate. Also, multiple impurity introduction operations can be achieved without resort to high temperatures. Exposure to high temperatures, as in thermal diffusion, disperses the impurities previously introduced. Ion implantation techniques permit greater control of the placement and depth of penetration into the semiconductor. In general, the total amounts of impurities introduced and the depths of penetration can be more closely controlled by ion implantation techniques than with thermal diffusion from conventional sources.
Consequently, integrated circuit devices can be made smaller, with greater precision, with better control of heating, and with higher operating speeds using ion implantation technology. As improvements in lithography permit smaller horizontal geometries the vertical dimensions of the semiconductor devices must also be compressed in order to achieve the highest performance. As the emiter junction become very shallow (e.g. .ltoreq.200 .eta.m) one experiences problems with junction passivation.
One facet of the ion implantation process is that the ions are implanted a finite distance into the silicon. Although there is also some lateral scattering under the mask edge, this is much smaller than the vertical penetration. Hence the vertical junction depth will always be greater than the horizontal displacement under the mask edge. Clearly the ratio of horizontal to vertical displacement becomes smaller as the junction becomes shallower, at least for the same implant conditions. Too small of a lateral extent of the emitter under the insulator results in a poorly passivated or shorted emitter-base junction.
This problem is even more serious for devices fabricated with dual dielectric surface insulators. A conventional technology employs a layer of Si.sub.3 N.sub.4 on top of a layer of SiO.sub.2 for the purposes of passivation and self alignment. In this case, the opening in the top insulating layer serves as an etch mask for the lower SiO.sub.2 layer. In order to guarantee that the contact is open to the silicon some over etching is necessary. Since the emitter dopant is supplied by a low energy (20 to 50 Kev.) arsenic implant, the upper insulator (usually Si.sub.3 N.sub.4) will mask the ions from the undercut region. During the drive in of the emitter a small amount of oxide must be grown (150-200 A) in order to prevent outdiffusion of the arsenic. This oxide must be removed which causes additional undercutting. If this accumulated undercutting is too severe compared with the lateral motion of the junction, then the junction will be poorly passivated or shorted. The shallower the emitter junction, the smaller the lateral motion of the dopant, and hence the tolerance to undercutting becomes more critical.
Also, the conventional methods of contacting the emitter region enhance the difficulty of passivating very shallow structures. To assure good electrical contact, it is essential to use a silicide contact layers such as, PtSi or Pd.sub.2 Si. These are formed by interacting the precious metal with the silicon. Thus, the boundary between the silicide and the silicon is even closer to the perimeter of the emitter base junction.
Still another problem is encountered in fabricating very shallow structures with conventional ion implantation techniques and that has to do with the damage to the crystal lattice caused by the implanted ions. The shallow structure requires a very small amount of thermal treatment to drive the dopant into the proper depth. This thermal treatment also must serve to anneal the implantation damage and it is insufficient for very shallow emitters. It is acknowledged that platinum silicide as a contact and/or interconnection to a silicon region in an integrated circuit device is well known in the art. See for example, U.S. Pat. No. 3,777,364, entitled "Methods For Forming Metal/Metal Silicide Semiconductor Device Interconnect System" granted Dec. 11, 1973 to R. D. Schinella et al.